1. Field of the Invention
The present invention relates to a frame sync detecting circuit which is suitably implemented in an FSK demodulator circuit or the like, and an FSK receiver using the same.
2. Description of the Related Art
In the FSK (Frequency Shift Keying) modulation scheme, demodulation is performed by frequency-voltage conversion. In this demodulation, voltages having levels corresponding to a plurality of (e.g., two or four) frequencies are output as a demodulated signal, and a DC offset is superimposed on the demodulated signal in connection with an error between transmitted and received frequencies. While, in a phase modulation scheme, demodulation is performed by phase-voltage conversion, and a DC offset also occurs in connection with an error between transmitted and received phases, the following description will be made based on only the FSK modulation scheme. If the DC offset is included, it will become difficult to detect a specific word pattern for frame synchronization or the like. This is particularly prominent in 4-level FSK where a symbol voltage interval (symbol frequency deviation interval) is narrow. Therefore, as a conventional technique of detecting a word pattern after performing offset correction, for example, JP 2006-339859A has been proposed.
In a sync signal detecting unit disclosed in JP 2006-339859A, in order to detect a frame sync word inserted in a given position of each frame, a product-sum operation-based correlation value between a detected signal and a known frame sync word is firstly calculated. Subsequently, if the correlation value has a peak value which is equal to or greater than a given threshold value, after the detected signal is determined to be a frame sync word candidate, a DC offset value is determined from an average value in the detected signal, and offset correction is performed by subtracting the DC offset value from the detected signal. Then, a vector error (square sum of errors) for all symbol data of the detected signal after the correction and the known frame sync word is calculated. If the vector error is less than a given threshold value, the sync signal detecting unit determines that the detected signal is an intended frame sync word, and therefore synchronization is established. In this way, synchronization can be accurately detected from an initial signal, while eliminating a response lag due to DC offset removal.
In the above conventional technique, a correlation between a detected signal and a known frame sync word is calculated, and then a DC offset value obtained from an average value in the detected signal is used for correction. Thus, a determination on a frame sync word candidate can be performed relatively rapidly, as described above. However, the correlation (convolution) processing is performed under a condition that the detected signal includes a DC offset, and thereby a threshold value for a final determination on frame synchronization establishment becomes lower. Consequently, noise or main data (in FSK, traffic channel) is liable to be erroneously determined as a frame sync word, which causes cases where it adversely takes longer time to establish synchronization.